CYW4343X
Table 48. SDIO Bus Timing a Parameters (Default Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO CLK (All values are referred to minimum VIH and maximum VILb)
Frequency—Data Transfer mode
Frequency—Identification mode
Clock low time
fPP
0
–
–
–
–
–
–
25
400
–
MHz
fOD
tWL
tWH
tTLH
tTHL
0
kHz
ns
10
10
–
Clock high time
–
ns
Clock rise time
10
10
ns
Clock fall time
–
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time—Data Transfer mode
tODLY
tODLY
0
0
–
–
14
50
ns
ns
Output delay time—Identification mode
a. Timing is based on CL 40 pF load on command and data.
b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
21.2 SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 52 and Table 49.
Figure 52. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Document No. 002-14797 Rev. *H
Page 113 of 128
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