CYW4343X
Table 49. SDIO Bus Timing a Parameters (High-Speed Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO CLK (all values are referred to minimum VIH and maximum VILb)
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
fPP
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
fOD
tWL
tWH
tTLH
tTHL
kHz
ns
Clock high time
–
ns
Clock rise time
3
ns
Clock fall time
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
6
2
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
tODLY
tOH
–
–
–
–
14
–
ns
ns
pF
2.5
–
Total system capacitance (each line)
a. Timing is based on CL 40 pF load on command and data.
b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
CL
40
21.3 gSPI Signal Timing
The gSPI device always samples data on the rising edge of the clock.
Figure 53. gSPI Timing
T1
T2
T4
T5
T3
SPI_CLK
SPI_DIN
T6
T7
T8
T9
SPI_DOUT
(falling edge)
Table 50. gSPI Timing Parameters
Minimum Maximum
Parameter
Clock period
Clock high/low
Clock rise/fall time
Symbol
Units
Note
T1
20.8
–
ns
Fmax = 50 MHz
T2/T3
T4/T5
(0.45 × T1) – T4
–
(0.55 × T1) – T4
2.5
ns
ns
–
–
Document No. 002-14797 Rev. *H
Page 114 of 128
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