PRELIMINARY
CYW43438
21.3 gSPI Signal Timing
The gSPI device always samples data on the rising edge of the clock.
Figure 37. gSPI Timing
T1
T2
T4
T5
T3
SPI_CLK
SPI_DIN
T6
T7
T8
T9
SPI_DOUT
(falling edge)
Table 44. gSPI Timing Parameters
Parameter
Clock period
Symbol
T1
Minimum
Maximum
Units
Note
20.8
–
(0.55 × T1) – T4
2.5
ns
ns
ns
F
–
–
= 50 MHz
max
Clock high/low
T2/T3
T4/T5
(0.45 × T1) – T4
–
Clock rise/fall time
Setup time, SIMO valid to SPI_CLK active
edge
Input setup time
Input hold time
T6
T7
T8
T9
5.0
5.0
5.0
5.0
–
–
–
–
ns
ns
ns
ns
Hold time, SPI_CLK active edge to SIMO
invalid
Setup time, SOMI valid before SPI_CLK
rising
Output setup time
Output hold time
Hold time, SPI_CLK active edge to SOMI
invalid
1
CSX to clock
–
–
7.86
–
–
–
ns
ns
CSX fall to 1st rising edge
c
Clock to CSX
Last falling edge to CSX high
1. SPI_CSx remains active for entire duration of gSPI read/write/write_read transaction (that is, overall words for multiple word transaction)
21.4 JTAG Timing
Table 45. JTAG Timing Characteristics
Output
Output
Signal Name
Period
125 ns
Setup
Hold
Maximum
Minimum
TCK
TDI
–
–
–
–
–
–
–
–
–
20 ns
20 ns
–
0 ns
0 ns
–
TMS
TDO
–
–
100 ns
–
0 ns
–
JTAG_TRST
250 ns
–
–
Document Number: 002-14796 Rev. *K
Page 92 of 101
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