PRELIMINARY
CYW43438
21.2 SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 36 and Table 43.
Figure 36. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Table 43. SDIO Bus Timing 1 Parameters (High-Speed Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO CLK (all values are referred to minimum VIH and maximum VIL2)
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
fPP
fOD
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
kHz
ns
tWL
tWH
tTLH
tTHL
Clock high time
–
ns
Clock rise time
3
ns
Clock fall time
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
6
2
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
tODLY
tOH
–
2.5
–
–
–
–
14
–
ns
ns
pF
Total system capacitance (each line)
CL
40
1. Timing is based on CL 40 pF load on command and data.
2. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
Document Number: 002-14796 Rev. *K
Page 91 of 101
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