PRELIMINARY
CYW43438
19.3 CLDO
Table 38. CLDO Specifications
Specification
Notes
Min. Typ. Max.
Units
Min. = 1.2 + 0.15V = 1.35V dropout voltage
requirement must be met under maximum load.
Input supply voltage, Vin
1.3
1.35
1.5
V
Output current
–
0.2
0.95
–
–
1.2
–
200
1.26
150
+4
–
mA
V
Output voltage, Vo
Dropout voltage
Programmable in 10 mV steps. Default = 1.2.V
At max. load
mV
%
Output voltage DC accuracy
Includes line/load regulation
No load
–4
–
–
13
1.24
–
µA
Quiescent current
200 mA load
–
–
mA
mV/V
mV/mA
µA
Line regulation
Load regulation
Vin from (Vo + 0.15V) to 1.5V, maximum load
Load from 1 mA to 300 mA
Power down
–
5
–
0.02 0.05
–
5
1
–
20
3
Leakage current
PSRR
Bypass mode
–
µA
@1 kHz, Vin ≥ 1.35V, Co = 4.7 µF
20
–
dB
VDDIO up and steady. Time from the REG_ON rising
edge to the CLDO
Start-up time of PMU
–
–
700
µs
reaching 1.2V.
LDO turn-on time
LDO turn-on time when rest of the chip is up.
–
1.11
140
2.2
180
–
µs
µF
External output capacitor, Co
Total ESR: 5 mΩ–240 mΩ
Only use an external input capacitor at the VDD_LDO
pin if it is not supplied from CBUCK output.
External input capacitor
–
1
2.2
µF
1. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document Number: 002-14796 Rev. *K
Page 86 of 101
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