PRELIMINARY
CYW43438
19. Internal Regulator Electrical Specifications
Note: Values in this data sheet are design goals and are subject to change based on device characterization results.
Functional operation is not guaranteed outside of the specification limits provided in this section.
19.1 Core Buck Switching Regulator
Table 36. Core Buck Switching Regulator (CBUCK) Specifications
Specification
Input supply voltage (DC)
PWM mode switching frequency
PWM output current
Notes
Min.
2.4
–
Typ.
3.6
4
Max.
4.81
–
Units
V
DC voltage range inclusive of disturbances.
CCM, load > 100 mA VBAT = 3.6V.
MHz
mA
mA
–
–
–
–
370
–
Output current limit
–
1400
Programmable, 30 mV steps.
Default = 1.35V.
Output voltage range
1.2
–4
1.35
–
1.5
4
V
PWM output voltage
DC accuracy
Includes load and line regulation.
Forced PWM mode.
%
Measure with 20 MHz bandwidth limit.
Static load, max. ripple based on VBAT = 3.6V,
Vout = 1.35V,
Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH, Cap
+ Board total-ESR < 20 mΩ,
PWM ripple voltage, static
–
7
20
mVpp
Cout > 1.9 μF, ESL<200 pH
Peak efficiency at 200 mA load, inductor DCR
= 200 mΩ, VBAT = 3.6V, VOUT = 1.35V
PWM mode peak efficiency
PFM mode efficiency
–
–
85
77
–
–
%
%
10 mA load current, inductor DCR = 200 mΩ,
VBAT = 3.6V, VOUT = 1.35V
VDDIO already ON and steady.
Time from REG_ON rising edge to CLDO
reaching 1.2V
Start-up time from
power down
–
400
500
µs
0603 size, 2.2 μH ±20%,
DCR = 0.2Ω ± 25%
External inductor
–
2.2
4.7
–
µH
µF
Ceramic, X5R, 0402,
ESR <30 mΩ at 4 MHz, 4.7 μF ±20%, 10V
External output capacitor
2.02
103
For SR_VDDBATP5V pin,
ceramic, X5R, 0603,
ESR < 30 mΩ at 4 MHz, ±4.7 μF ±20%, 10V
External input capacitor
0.672
40
4.7
–
–
–
µF
µs
Input supply voltage ramp-up time
0 to 4.3V
1. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
2. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
3. Total capacitance includes those connected at the far end of the active load.
Document Number: 002-14796 Rev. *K
Page 84 of 101
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