CYW43362
12. Internal Regulator Electrical Specifications
Note: Values in this document are design goals and are subject to change based on the results of device characterization.
Functional operation is not guaranteed outside the specification limits provided in this section.
12.1 Core Buck Regulator
The specifications for the Core Buck regulator (CBUCK) are provided in Table 20.
Table 20. Core Buck Regulator
Specification
Notes
Minimum Typical Maximum Units
4.8a
3.84
Input supply voltage
–
–
2.3
–
Volts
MHz
PWM mode switching
frequency
2.56
3.2
PWM output current
Output current limit
Output voltage range
–
–
–
–
500
–
mA
–
700
–
mA
Programmable, 33.33 mV steps
default = 1.8V
1.2
1.833
Volts
Output voltage DC accuracy Includes load and line regulation. VBAT = 2.7V to 4.8V, –5
–
7
5
%
Load 0 to 500 mA, Inductor DCR < 137.5 mΩ
PWM ripple voltage, staticb
Measure with 20 MHz BW limit.
Fixed load (0 to 500 mA).
–
20
mVpp
Max ripple based on VBAT < 4.3V, Vout = 1.833V, Fs =
3.2 MHz, 1.5 µH inductor L > 0.6144 µH, Cap+Board
total-ESR < 10 mΩ, Cout > 1.9 µF
PWM load step transient
voltage error
VBAT = 2.7V to 4.8V,
–
–
100
50
200
100
mV
mV
current step = 150 to 400 mA,
1 µsec rise-time based on 0402, 6.3V,
X5R, and 4.7 µFc ceramic capacitor.
PWM line step
transient voltage error
VBAT step from 2.3 to 2.7V,
10 µsec rise-time,
fixed 500 mA load based on 0402, 6.3V,
X5R, and 4.7 µFb ceramic capacitor.
PWM load regulationa
PWM line regulationa
VBAT = 2.7V to 4.8V,
–
–
–
–
+30
+10
mV
mV
10 mA to 500 mA load.
Inductor DCR < 137.5 mΩ
VBAT = 2.7V to 4.8V,
500 mA load.
Inductor DCR < 137.5 mΩ
Burst mode ripple voltage,
static
Load < 30 mA.
Measure with 20 MHz BW limit.
–
–
–
–
80
mVpp
mVpp
mV
30 mA < Load < 200 mA.
Measure with 20 MHz BW limit.
–
200
120
Burst mode load step transient VBAT = 2.7V to 4.8V,
voltage error
60
current step 10 to 200 mA,
1 µsec rise-time based on 0402, 6.3V,
X5R, and 4.7 µFb ceramic capacitor.
Burst mode line step transient VBAT step from 2.3V to 2.7V,
–
50
35
100
50
mV
voltage error
10 µsec rise-time, fixed 200 mA load based on 0402,
6.3V, X5R, and 4.7 µFb ceramic capacitor.
Burst mode load regulation
VBAT = 2.7V to 4.8V,
10 mA to 200 mA load
–
–
mV
mV
Burst line regulation
Input voltage 2.7 to 4.8V, 200 mA load
44
90
70
–
Peak PWM mode efficiencyd
200 mA load current
30 mA load current
80
60
%
%
Burst mode efficiency
5 mA load current
70
80
–
%
Document No. 002-14779 Rev. *G
Page 48 of 60
CYPRESS [ CYPRESS ]
