PRELIMINARY
CYW43340
Table 17. WLBGA Signal Descriptions (Cont.)
WLBGA Ball
Signal Name
Type
Description
Bluetooth UART and Wake
G11
H11
H10
G10
E10
F10
BT_UART_CTS_N
BT_UART_RTS_N
BT_UART_RXD
BT_UART_TXD
BT_DEV_WAKE
BT_HOST_WAKE
I
UART clear-to-send. Active-low clear-to-send
signal for the HCI UART interface.
O
UART request-to-send. Active-low request-to-
send signal for the HCI UART interface.
I
UART serial input. Serial data input for the HCI
UART interface.
O
UART serial output. Serial data output for the
HCI UART interface.
I/O
I/O
DEV_WAKE or general-purpose
I/O signal
HOST_WAKE or general-purpose I/O signal
Note: By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART
functionality. Through software configuration, the PCM interface can also be routed over the
BT_WAKE/UART signals as follows:
■ PCM_CLK on the UART_RTS_N pin
■ PCM_OUT on the UART_CTS_N pin
■ PCM_SYNC on the BT_HOST_WAKE pin
■ PCM_IN on the BT_DEV_WAKE pin
In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire
UART Transport.
Bluetooth/FM I2S
D7
E7
D8
BT_I2S_CLK
BT_I2S_DO
BT_I2S_WS
I/O
I/O
I/O
I2S clock; can be master (output) or slave (input)
I2S data output
I2S WS; can be master (output) or slave (input)
Miscellaneous
J1
WL_REG_ON
I
Used by PMU to power up or power down the
internal CYW43340 regulators used by the
WLAN section. Also, when deasserted, this pin
holds the WLAN section in reset. This pin has
an internal 200 k pull-down resistor that is
enabled by default. It can be disabled through
programming.
J2
BT_REG_ON
I
Used by PMU to power up or power down the
internal CYW43340 regulators used by the
Bluetooth/FM section. Also, when deasserted,
this pin holds the Bluetooth/FM section in reset.
This pin has an internal 200 k pull-down
resistor that is enabled by default. It can be
disabled through programming.
Document Number: 002-14943 Rev. *L
Page 49 of 96
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