PRELIMINARY
CYW43340
12. Pinout and Signal Descriptions
12.1 Signal Assignments
Figure 27 shows the WLBGA ball map. Table 17 on page 46 contains the signal description for all packages.
Figure 27. 141-Bump CYW43340 WLBGA Ball Map (Bottom View)
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
FM_LNAVCOVDD FM_RFIN
BT_VCOVDD BT_LNAVDD
BT_VCOVSS BT_PLLVDD
FM_PLLVSS BT_IFVDD
BT_I2S_WS
BT_RF
BT_PAVDD
WRF_RFIN_2G
WRF_RFOUT_2G
WRF_PAPMU_VOUT_LDO3P3
WRF_RFOUT_5G
WRF_PAPMU_VBAT_VDD5P0
WRF_PAPMU_GND
A
B
C
D
E
F
FM_VCOVSS
FM_AOUT2
FM_AOUT1
CLK_REQ
LPO_IN
FM_LNAVSS
BT_PAVSS
BT_IFVSS
VSSC_D6
WRF_PA2G_VBAT_VDD3P3
WRF_CBUCK_PAVDD1P5
BT_PLLVSS
BT_I2S_CLK
BT_I2S_DO
BT_PCM_SYNC
WRF_PA2G_VBAT_GND3P3
WRF_PA5G_VBAT_GND3P3_C3 WRF_PA5G_VBAT_GND3P3_C2 WRF_RFIN_5G
FM_PLLVDD
WRF_LNA_2G_GND1P2
WRF_RX_GND1P2
WRF_PADRV_VBAT_VDD3P3 WRF_PADRV_VBAT_GND3P3
WRF_TX_GND1P2
WRF_GPIO_OUT
WRF_LNA_5G_GND1P2
WRF_VCO_GND1P2
WRF_XTAL_CAB_VDD1P2
WRF_XTAL_CAB_XOP
WRF_XTAL_CAB_XON
WL_REG_ON
BT_DEV_WAKE VDDC_E9
BT_HOST_WAKE BT_PCM_IN BT_PCM_CLK
NC_G9
BT_UART_RTS_N BT_UART_RXD VDDIO_H9
BT_PCM_OUT
WRF_AFE_GND1P2
WRF_BUCK_VDD1P5
WL_GPIO_2
WL_GPIO_1
WRF_SYNTH_VDD1P2
WRF_SYNTH_GND1P2
WRF_XTAL_CAB_GND1P2
BT_REG_ON
G
H
J
BT_UART_CTS_N BT_UART_TXD
RF_SW_CTRL_3 VSSC_G7
RF_SW_CTRL_4 VDDC_H7
RF_SW_CTRL_2 WL_GPIO_6
RF_SW_CTRL_1 WL_GPIO_5
WL_GPIO_0
G
H
J
WL_GPIO_3
WRF_TCXO_VDD1P8
WRF_TCXO_CKIN2V
RREFHSIC
NC_J11
VSS_J10
VSS_K10
VSS_L10
VSS_M10
VSS_N10
NC_J9
VSS_J8
VSS_K8
VSS_L8
VSS_M8
VSS_N8
WL_GPIO_4
NC_K7
VDDIO_RF
WL_GPIO_12
VDDIO_J4
K
L
VSS_K11
VSS_L11
VSS_M11
VSS_N11
VSS_P11
NC_K9
VSS_L9
VSS_M9
VSS_N9
SDIO_DATA_2
SDIO_DATA_3
SDIO_DATA_1
JTAG_SEL
HSIC_DATA
VDDC_K1
K
L
NC_L7
RF_SW_CTRL_0 SDIO_DATA_0
HSIC_DVDD1P2_OUT
HSIC_STROBE
HSIC_AGND12PLL
PMU_AVSS
M
N
P
NC_M7
SDIO_CLK
VSSC_N6
SDIO_CMD
VDDC_P5
VSSC_M2
M
N
P
VSS_N7
VOUT_2P5
VOUT_CLDO
SR_VDDBATA5V
SR_VLX
VSS_P10
10
VSS_P9
9
VSS_P8
8
VSS_P7
7
VSS_P6
6
VOUT_LNLDO
4
LDO_VDD1P5
3
SR_VDDBATP5V
2
SR_PVSS
1
11
5
Top layer metal restrict
Depopulated
12.2 Signal Descriptions
The signal name, type, and description of each pin in the CYW43340 is listed in Table 17. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input,
O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. See also Table 18 on page
53 for resistor strapping options.
Document Number: 002-14943 Rev. *L
Page 45 of 96
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