PRELIMINARY
CYW43340
Table 17. WLBGA Signal Descriptions
WLBGA Ball
Signal Name
Type
Description
WLAN RF Signal Interface
A5
C1
A4
A2
D2
WRF_RFIN_2G
I
2.4G RF input
5G RF input
2.4G RF output
5G RF output
–
WRF_RFIN_5G
I
WRF_RFOUT_2G
WRF_RFOUT_5G
WRF_GPIO_OUT
O
O
I/O
RF Control Signals
L6
RF_SW_CTRL_0
RF_SW_CTRL_1
RF_SW_CTRL_2
RF_SW_CTRL_3
RF_SW_CTRL_4
O
RF switch enable
RF switch enable
RF switch enable
RF switch enable
RF switch enable
H6
G6
G8
H8
O
O
O
O
SDIO Bus Interface
M6
M5
L5
SDIO_CLK
I
SDIO clock input
SDIO_CMD
I/O
I/O
I/O
SDIO command line
SDIO data line 0
SDIO_DATA_0
SDIO_DATA_1
L4
SDIO data line 1. Also used as a strapping
option (see Table 18 on page 53).
K5
K4
SDIO_DATA_2
SDIO_DATA_3
I/O
I/O
SDIO data line 2. Also used as a strapping
option (see Table 18 on page 53).
SDIO data line 3
Note: Per Section 6 of the SDIO specification, 10 to 100 kohm pull-ups are required on the four DATA lines and the CMD
line. This requirement must be met during all operating states by using external pull-up resistors or properly
programming internal SDIO Host pull-ups.
JTAG Interface
M4
JTAG_SEL
I/O
JTAG select: Connect this pin high (VDDIO) in
order to use GPIO_2 through GPIO_5 and
GPIO_12 as JTAG signals. Otherwise, if this pin
is left as a NO_CONNECT, its internal pull-down
selects the default mode that allows GPIOs 2,
3, 4, 5, and 12 to be used as GPIOs.
Note: See “WLAN GPIO Interface” on
page 47 for the JTAG signal pins.
HSIC Interface
L2
K2
K3
HSIC_STROBE
HSIC_DATA
RREFHSIC
I
HSIC Strobe
HSIC Data
I/O
I
HSIC reference resistor input. If HSIC is used,
connect this pin to ground via a 51Ω 5% resistor.
Document Number: 002-14943 Rev. *L
Page 46 of 96
CYPRESS [ CYPRESS ]
