PRELIMINARY
CYW43340
12.2.1 WLAN GPIO Signals and Strapping Options
The pins listed in Table 18 on page 53 are sampled at power-on reset (POR) to determine the various operating modes. Sampling
occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or
alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD)
resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND,
using a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 18. WLAN GPIO Functions and Strapping Options (Advance Information)
WLBGA
Pin Name
Default
Function
Description
Pin #
SDIO_DATA_1
F9
0
strap_host_ifc_1
The three strap pins strap_host_ifc_[3:1] select the
host interfacea to enable:
■ 0XX: SDIO
■ 10X: xx
■ 110: normal HSIC
■ 111: bootloader-less HSIC
■ 1: select SDIO mode
■ 0: select SDIO mode
■ 1: select HSIC mode
SDIO_DATA_2
G8
J6
0
0
strap_host_ifc_2
strap_host_ifc_3
GPIO_6/
MODE_SEL
JTAG_SEL
M4
N/A
JTAG select
■ JTAGselect:Connectthispinhigh(VDDIO)inorder
to use GPIO_2 through GPIO_5 and GPIO_12 as
JTAG signals. Otherwise, if this pin is left as a
NO_CONNECT, its internal Pull-down selects the
default mode that allows GPIOs 2, 3, 4, 5, and 12
to be used as GPIOs.
Note: See “WLAN GPIO Interface” on page 47
for the JTAG signal pins.
a.The unused host interface is tristated. However, the SDIO lines have internal pulls activated when in HSIC mode (see Table 20: “I/O States,” on page 54).
There are no bus-keepers on the HSIC interface when it is not in use.
Document Number: 002-14943 Rev. *L
Page 53 of 96
CYPRESS [ CYPRESS ]
