PRELIMINARY
CYW43340
Table 17. WLBGA Signal Descriptions (Cont.)
WLBGA Ball
Signal Name
WLAN GPIO Interface
I/O
Type
Description
G3
F3
WL_GPIO_0
WL_GPIO_1
This pin can be programmed by software to be
a GPIO.
I/O
This pin can be programmed by software to be
a GPIO or an AP_READY or
HSIC_HOST_READY input from the host
indicating that it is awake.
G4
WL_GPIO_2
I/O
This pin can be programmed by software to be
a GPIO, the JTAG TCK or an HSIC_READY
output to the host, indicating that the device is
ready to respond with a CONNECTwhen it sees
IDLE on the HSIC bus.
H4
J7
WL_GPIO_3
WL_GPIO_4
I/O
I/O
This pin can be programmed by software to be
a GPIO or the JTAG TMS signal.
This pin can be programmed by software to be
a GPIO, the JTAG TDI signal, the UART RX
signal, or as the
WLAN_HOST_WAKE output indicating
that host wake-up should be performed.
H5
G5
WL_GPIO_5
WL_GPIO_6
I/O
I/O
This pin can be programmed by software to be
a GPIO, the JTAG TDO signal or the UART TX
signal.
GPIO pin.
Note: Some GPIOs are also used as
strapping options (see Table 18 on page
53).
J5
WL_GPIO_12
I/O
This pin can be programmed by software to be
a GPIO or the JTAG TRST_L signal. GPIO12
has an internal pull-down by default if
JTAG_SEL is low. When JTAG_SEL is high,
GPIO12 is used as JTAG_TRST_Land is pulled
up.
This pin is also used as WLAN_DEV_WAKE, an
out-of- band wake-up signal when the host
wants to wake WLAN from the deep sleep
mode.
Note: Some GPIOs are also used as
strapping options (see Table 18 on page
53).
Document Number: 002-14943 Rev. *L
Page 47 of 96
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