BCM4330 Preliminary Data Sheet
Signal Assignments
Table 18: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)
Bump#
WLCSP Signal Name
Ball#
FCFBGA WLBGA
Type Description
Integrated Switching Regulators
L12, K12 L12, K12 76–80
SR_VDDBAT1
SR_VDDBAT2
SR_VLX
I
I
O
Buck regulator: Battery Voltage Input
Core buck regulator: output to inductor
K11
K11
81–85
86–90
L11, M12 M12
WLAN SDIO Bus Interface
L7
M6
M8
M5
L8
M7
L7
177
178
179
180
175
176
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
SDIO_CLK
I/O
I/O
I/O
I/O
I
SDIO data line 0
SDIO data line 1
SDIO data line 2
SDIO data line 3
SDIO clock
M5
M8
L8
M6
M7
SDIO_CMD
I/O
SDIO command line
JTAG Interface
L5
F5
165
JTAG_SEL
I
JTAG selection pin (pulled HIGH by
default)
–
–
–
–
–
–
–
–
–
–
–
–
TCK
TDI
TDO
TMS
I
I
I
I
These JTAG signals can be enabled by
software on pins WL_GPIO[1:5].
TMS
WL_GPIO1
WL_GPIO2
WL_GPIO3
WL_GPIO4
WL_GPIO5
TCK
TDI
TDO
TRST_L
HSIC Interface
K1
L1
M2
L2
164
162
163
HSIC_STROBE
HSIC_DATA
HSIC_RREF
I/O
I/O
I
HSIC bidirectional data strobe signal.
HSIC terminations are built in, external
resistors are not needed. On SDIO
designs this pin should not be
connected.
HSIC bidirectional DDR data signal.
HSIC terminations are built in, external
resistors are not needed. On SDIO
designs this pin should not be
connected.
L2
J1
HSIC bias pin. Connect to ground via a
49.9 Ohm series resistor. On SDIO
designs this pin should not be
connected.
Clocks
F1
G1
F2
G1
H1
G3
41
40
36
WRF_XTAL_OP
WRF_XTAL_ON
WRF_TCXO_IN
I
O
I
Crystal oscillator input
Crystal oscillator output
External TCXO input
®
BROADCOM
BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 106