BCM4319 Preliminary Data Sheet
SDIO High Speed Mode Timing
Table 29: SDIO Bus Timing a Parameters (High-Speed Mode)
Parameter
Symbol
Minimum Typical
Maximum Unit
b
SDIO CLK (all values are referred to minimum VIH and maximum VIL )
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
fPP
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
kHz
ns
fOD
tWL
tWH
tTLH
tTHL
Clock high time
–
ns
Clock rise time
3
ns
Clock low time
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup Time
tISU
tIH
6
2
–
–
–
–
ns
ns
Input hold Time
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
tODLY
tOH
–
–
–
–
14
–
ns
ns
pF
2.5
–
Total system capacitance (each line)
CL
40
a. Timing is based on CL ≤ 40pF load on CMD and Data.
b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.
Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 77
April 2, 2014 • 4319-DS05-R
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