BCM4319 Preliminary Data Sheet
Reset and Regulator Control Signal Sequencing
Figure 21: Power-Up Sequence Timing Diagram
VBAT and VDDIO present (order is immaterial)
VBAT
150 ms
100 ms
VDDIO
> 100 us
WL_REG_ON
EXT_POR_L
> 100 us
25 ms
USB
Attach
Ready to respond
to SDIO access
GPIO
Strapping values,
latched in this window
O/P Pins
Z
Actively driven
NOTES:
EXT_POR_L should be low when VDDIO is absent.
VBAT must be either powered ON (2.7—5.5V) or OFF (0V): it cannot be left floating.
Recommend that WL_REG_ON be LOW when VBAT is 0V.
WL_REG_ON and EXT_POR_L can be tied together and should be low when either VBAT or VDDIO is low.
Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 73
April 2, 2014 • 4319-DS05-R
CYPRESS [ CYPRESS ]
