BCM4319 Preliminary Data Sheet
SDIO High Speed Mode Timing
Table 28: SDIO Bus Timing a Parameters (Default Mode) (Cont.)
Parameter
Symbol
Minimum Typical
Maximum Unit
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
Output delay time – Identification mode
tODLY
tODLY
0
0
–
–
14
50
ns
ns
a. Timing is based on CL ≤ 40pF load on CMD and Data.
b. min(Vih) = 0.7 × VDDIO_SD and max(Vil) = 0.2 × VDDIO_SD.
SDIO High Speed Mode Timing
SDIO high speed mode timing is shown by the combination of Figure 24 and Table 29.
Figure 24: SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Broadcom®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 76
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