BCM4319 Preliminary Data Sheet
SDIO Default Mode Timing
Table 27: gSPI Timing
Parameter
Symbol Minimum
Maximum
Units Note
ns Last falling edge to CSX high
Clock to CSXa
–
–
–
a. SPI_CSx remains active for entire duration of SPI read/write/write_read transaction (i.e., overall words for
multiple word transaction).
SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 23 and Table 28 on page 75.
Figure 23: SDIO Bus Timing (Default Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tODLY
(max)
(min)
Table 28: SDIO Bus Timing a Parameters (Default Mode)
Parameter
Symbol
Minimum Typical
Maximum Unit
SDIO CLK (All values are referred to minimum VIH and maximum VILb)
Frequency – Data Transfer mode
Frequency – Identification mode
Clock low time
fPP
0
–
–
–
–
–
–
25
400
–
MHz
kHz
ns
fOD
tWL
tWH
tTLH
tTHL
0
10
10
–
Clock high time
–
ns
Clock rise time
10
10
ns
Clock low time
–
ns
Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 75
April 2, 2014 • 4319-DS05-R
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