BCM4319 Preliminary Data Sheet
Interface Timing Specifications
Section 14: Interface Timing
Specifications
This section describes the interface timing for gSPI, SDIO (default), and SDIO high-speed modes.
gSPI TIMING
The gSPI host and device always use the rising edge of the clock to sample data.
Figure 22: gSPI Timing
Table 27: gSPI Timing
Parameter
Symbol Minimum
Maximum
Units Note
ns Fmax = 48 MHz
Clock period
Clock high/low
T1
20.8
–
T2/T3
(0.45 × T1) – (0.55 × T1) – ns
–
T4
T4
2.5
–
Clock rise/fall time T4/T5
Input setup time T6
–
ns
ns
–
5.0
Setup time, SIMO valid to SPI_CLK active
edge
Input hold time
T7
5.0
5.0
5.0
7.86
–
–
–
–
ns
ns
ns
ns
Hold time, SPI_CLK active edge to SIMO
invalid
Output setup time T8
Output hold time T9
Setup time, SOMI valid before SPI_CLK
rising
Hold time, SPI_CLK active edge to SOMI
invalid
CSX to clocka
–
CSX fall to 1st rising edge
Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 74
April 2, 2014 • 4319-DS05-R
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