CYW20732A0
Figure 10. UART Timing
3.3.2 SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz when 2.2V > VDDIO
≥ 1.62V.
Table 19. SPI Interface Timing Specifications
Reference
Characteristics
Time from CSN asserted to first clock edge
Master setup time
Min
1 SCK
Typ
Max
1
2
3
4
5
6
100
∞
–
–
½ SCK
–
Master hold time
½ SCK
–
–
Slave setup time
½ SCK
–
–
Slave hold time
½ SCK
1 SCK
–
Time from last clock edge to CSN deasserted
10 SCK
100
Figure 11 and Figure 12 on page 26 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3,
respectively.
Document Number: 002-14837 Rev. *L
Page 25 of 35
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