CYW20732A0
Figure 11. SPI Timing – Mode 0 and 2
6
SPI_CSN
SPI_CLK
1
(Mode 0)
SPI_CLK
(Mode 2)
2
3
‐
First Bit
Second Bit
Last bit
Last bit
‐
SPI_MOSI
SPI_MISO
4
5
First Bit
Not Driven
Second Bit
Not Driven
Figure 12. SPI Timing – Mode 1 and 3
6
SPI_CSN
SPI_CLK
1
(Mode 1)
SPI_CLK
(Mode 3)
2
3
‐
Invalid bit
Invalid bit
‐
First bit
Last bit
Last bit
SPI_MOSI
SPI_MISO
4
5
Not Driven
Not Driven
First bit
3.3.3 BSC Interface Timing
Table 20. BSC Interface Timing Specifications
Reference
Characteristics
Min
Max
100
Unit
kHz
1
Clock frequency
–
400
800
1000
–
2
3
4
5
6
START condition setup time
START condition hold time
Clock low time
650
280
650
280
0
ns
ns
ns
ns
ns
–
–
Clock high time
Data input hold timea
–
–
Document Number: 002-14837 Rev. *L
Page 26 of 35
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