CYW20732A0
Table 20. BSC Interface Timing Specifications
Reference
Characteristics
Min
100
Max
Unit
7
Data input setup time
STOP condition setup time
Output valid from clock
Bus free timeb
–
–
ns
ns
ns
ns
8
280
–
9
400
–
10
650
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START
or STOP conditions.
b. Time that the cbus must be free before a new transaction can start.
Figure 13. BSC Interface Timing Diagram
Document Number: 002-14837 Rev. *L
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