PRELIMINARY
CYW20710
Table 25. PCM Interface Timing Specifications (Long Frame Synchronization, Master Mode)
Reference
Characteristics
Minimum
128
Maximum
Unit
kHz
1
PCM bit clock frequency
PCM bit clock HIGH time
PCM bit clock LOW time
2048
–
2
3
4
209
209
–
ns
ns
ns
–
Delay from PCM_BCLK rising edge to PCM_SYNC HIGH during first bit
time
50
5
Delay from PCM_BCLK rising edge to PCM_SYNC LOW during third bit
time
–
50
ns
6
7
8
9
Delay from PCM_BCLK rising edge to data valid on PCM_OUT
Setup time for PCM_IN before PCM_BCLK falling edge
Hold time for PCM_IN after PCM_BCLK falling edge
–
50
–
ns
ns
ns
ns
50
10
–
Delay from falling edge of PCM_BCLK during last bit period to PCM_OUT –
becoming high impedance
50
Figure 15. PCM Interface Timing (Long Frame Synchronization, Master Mode)
2
1
3
PCM_BCLK
PCM_SYNC
4
5
6
9
HIGH
IMPEDENCE
Bit 0
Bit 1
Bit 2
Bit 15
PCM_OUT
PCM_IN
7
8
Bit 0
Bit 1
Bit 2
Bit 15
Document No. 002-14804 Rev. *H
Page 42 of 50
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