PRELIMINARY
CYW20710
9.2 Timing and AC Characteristics
In this section, use the numbers listed in the reference column to interpret the timing diagrams.
9.2.1 Startup Timing
There are two basic startup scenarios. In one scenario, the chip startup and firmware boot is held off while the RST_N pin is asserted.
In the second scenario, the chip startup and firmware boot is directly triggered by the chip power-up. In this case, an internal power-
on reset (POR) is held for a few ms, after which the chip commences startup.
The global reset signal in the CYW20710 is a logical OR (actually a wired AND, since the signals are active low) of the RST_N input
and the internal POR signals. The last signal to be released determines the time at which the chip is released from reset. The POR
is typically asserted for 3 ms after VDDC crosses the 0.8V threshold, but it may be as soon as 1.5 ms after this event.
After the chip is released from reset, both startup scenarios follow the same sequence, as follows:
1. After approximately 120 μs, the CLK_REQ (GPIO_5) signal is asserted.
2. The chip remains in sleep state for a minimum of 4.2 ms.
3. If present, the TCXO and LPO clocks must be oscillating by the end of the 4.2 ms period.
If a TCXO clock is not in the system, a crystal is assumed to be present at the XIN and XOUT pins. If an LPO clock is not used, the
firmware will detect the absence of a clock at the LPO_IN lead and use the internal LPO clock instead.
Figure 10 and Figure 11 illustrate the two startup timing scenarios.
Figure 10. Startup Timing from RST_N
tra m
= 2 0 0
μ s
p m a x
V D D IO , V B A T ,R E G _ E N *
V R E G
V D D C
> 0 .8 V
t
=
3 0 0
μ s
R S T _ N
t
= 6 4 to 1 7 1 μ s
G P IO 5 (C L K _ R E Q )
tm
= 4 .2 m s
a x
T C X O
L P O
Figure 11. Startup Timing from Power-on Reset
trampmax = 200 μs
VDDIO, VBAT,REG_EN*
VREG
VDDC > 0.8V
t = 300 μs
tmin= 1.5 ms
Internal POR
μs
t = 64 to 171
GPIO5 (CLK_REQ)
tmax = 4.2 ms
TCXO
LPO
Document No. 002-14804 Rev. *H
Page 38 of 50
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