PRELIMINARY
CYW20710
Table 26. PCM Interface Timing Specifications (Long Frame Synchronization, Slave Mode)
Reference
Characteristics
Minimum
128
Maximum
Unit
kHz
1
2
3
4
PCM bit clock frequency.
PCM bit clock HIGH time.
PCM bit clock LOW time.
2048
209
209
–
–
–
ns
ns
ns
Setup time for PCM_SYNC before falling edge of PCM_BCLK during first 50
bit time.
5
6
Hold time for PCM_SYNC after falling edge of PCM_BCLK during second 10
bit period. (PCM_SYNC may go low any time from second bit period to last
bit period).
–
ns
ns
Delay from rising edge of PCM_BCLK or PCM_SYNC
(whichever is later) to data valid for first bit on PCM_OUT.
–
50
7
8
9
Hold time of PCM_OUT after PCM_BCLK falling edge.
Setup time for PCM_IN before PCM_BCLK falling edge.
Hold time for PCM_IN after PCM_BCLK falling edge.
–
175
–
ns
ns
ns
ns
50
10
–
–
10
Delay from falling edge of PCM_BCLK or PCM_SYNC
(whichever is later) during last bit in slot to PCM_OUT becoming high
impedance.
100
Figure 16. PCM Interface Timing (Long Frame Synchronization, Slave Mode)
2
1
PCM_BCLK
PCM_SYNC
3
4
5
7
6
10
HIGH
IMPEDENCE
Bit 0
Bit 1
Bit 15
PCM_OUT
PCM_IN
8
9
Bit 0
Bit 1
Bit 15
Document No. 002-14804 Rev. *H
Page 43 of 50
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