PRELIMINARY
CYW20710
9.2.4 BSC Interface Timing
Table 27. BSC Interface Timing Specifications
Reference
Characteristics
Minimum
Maximum
Unit
kHz
1
Clock frequency
–
100
400
800
1000
2
3
4
5
6
7
8
9
START condition setup time
START condition hold time
Clock low time
650
280
650
280
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
Clock high time
–
Data input hold time1
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time2
–
100
280
–
–
–
400
–
10
650
1. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of
START or STOP conditions
2. Time that the cbus must be free before a new transaction can start.
Figure 17. BSC Interface Timing Diagram
1
5
SCL
2
4
7
8
6
3
SDA
IN
10
9
SDA
OUT
Document No. 002-14804 Rev. *H
Page 44 of 50
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