PRELIMINARY
CYW20710
Table 8. CYW20710 Signal Descriptions (Cont.)
FPBGA
50-Ball
WLBGA
Signal
42-Bump
I/O
Power Domain
Description
Serial flash SPI clock
SPIM_CLK
SPIM_CS_N
PCM_IN
A8
C7
F6
G6
F4
F5
B6
E4
E5
–
C1
E2
D4
E4
C4
A4
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
Serial flash active-low chip select
PCM/I2S data input
PCM/I2S data output
PCM/I2S clock
PCM_OUT
PCM_CLK
PCM_SYNC
COEX_IN
PCM sync/I2S word select
Coexistence input
COEX_OUT0
COEX_OUT1
OTP_DIS
–
Coexistence output
–
Coexistence output
A2
OTP disable pin. By default, leave this pin
floating.
Supplies
VDDIF
VDDTF
VDDLNA
VDDRF
VDDPX
VDDC
VDDC
VDDC
VDDO
VDDO
VDDO
NC
B1
C1
E1
F1
G1
A5
B8
F8
G5
A6
G8
–
–
I
I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Radio IF PLL supply
Radio PA supply
Radio LNA supply
Radio supply
B7
–
I
E7
F7
A3
F1
–
I
I
Radio RF PLL supply
Core logic supply
Core logic supply
Core logic supply
Digital I/O supply voltage
Digital I/O supply voltage
Digital I/O supply voltage
No connect
I
I
I
D3
–
I
I
–
I
B1
D7
B6
E6
F6
F3
A1
–
I
VSS
C2
D2
F2
D3
C6
A7
G7
–
–
–
–
–
–
–
–
–
Ground
VSS
Ground
VSS
Ground
VSS
Ground
VSS
Ground
VSS
Ground
VSS
Ground
VSS
B2
Ground
Document No. 002-14804 Rev. *H
Page 27 of 50
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