PRELIMINARY
CYW20710
7. Pin-Out and Signal Descriptions
7.1 Pin Descriptions
Table 8. CYW20710 Signal Descriptions
FPBGA
50-Ball
WLBGA
42-Bump
Signal
Radio
I/O
Power Domain
Description
RES
G4
D6
O
VDD_RF
External calibration resistor,
15 kΩ @ 1%
RFP
D1
G2
G3
C7
F5
E5
I/O
I
VDD_RF
VDD_RF
VDD_RF
RF I/O antenna port
XIN
Crystal or reference input
Crystal oscillator output
XOUT
O
Analog
LPO_IN
Voltage Regulators
REG_EN
VBAT
A4
B4
I
VDDRF
External LPO input
B2
A3
A2
A1
B5
A5
A6
A7
I
I
VDDO
N/A
HV LDO and main enable
HV LDO input
VREGHV
VREG
I/O
O
N/A
HV LDO output: main LDO input
Main LDO output
N/A
Straps
RST_N
TM0
B4
C4
–
C5
–
I
I
I
I
VDDO
VDDO
VDDO
VDDO
Active-low reset input
Clock request polarity select
Internally connected to ground
Reserved: connect to ground.
TM1
–
TM2
F3
C6
Digital I/O
GPIO_0
GPIO_1
GPIO_2
GPIO_3
B5
B3
–
C3
B3
–
I/O
I/O
I/O
I/O
VDDO
VDDO
VDDO
VDDO
GPIO/BT_WAKE
GPIO/HOST_WAKE
GPIO
–
–
GPIO/LINK_IND
Note: Can be configured for active high or low
as well as open drain.
GPIO_4
GPIO_5
–
–
I/O
I/O
VDDO
VDDO
GPIO
E6
F4
GPIO/CLK_REQ
TCXO-OR Function Out available on some
packages. See Section 11.“Ordering
Information”.
GPIO_6
E3
D5
I/O
VDDO
GPIO
TCXO-OR Function In available on some
packages. See Section 11.“Ordering
Information”.
GPIO_7
B7
D8
C8
D7
E8
F7
E7
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
DETATCH/CARD_DETECT
UART receive data
UART transmit data
UART request to send output
UART clear to send input
I2C clock
UART_RXD
UART_TXD
UART_RTS_N
UART_CTS_N
SCL
D2
C2
F2
E3
E1
D1
SDA
I2C data
Document No. 002-14804 Rev. *H
Page 26 of 50
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