PRELIMINARY
CYW20710
8. Ball Grid Arrays
Figure 8 shows the top view of the 50-ball 4.5 x 4 x 0.6 mm (FPBGA).
Figure 8. 50-Ball 4.5 x 4 x 0.6 mm (FPBGA) Array
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
Table 9. Ball-Out for the 50-Ball CYW20710A1KUFBXG
1
2
3
4
5
6
7
8
VREG
VREGHV VBAT
LPO_IN
VDDC
VDDO
VSS
GPIO_7
SPIM_CLK
A
B
C
D
E
F
VDDIF
REG_EN GPIO_1
RST_N
TM0
–
GPIO_0
COEX_IN
VDDC
VDDTF VSS
RFP VSS
–
–
–
VSS
–
SPIM_CS_N UART_TXD
UART_RTS_N UART_RXD
VSS
GPIO6
TM2
XOUT
VDDLNA –
COEX_OUT0 COEX_OUT1 GPIO_5
SDA
SCL
VSS
UART_CTS_N
VDDC
VDDRF VSS
VDDPX XIN
PCM_CLK
RES
PCM_SYNC PCM_IN
VDDO PCM_OUT
VDDO
G
Figure 9 shows the top view of the 42-bump, 2.97 x 2.46 x 0.5 mm array.
Figure 9. 42-Bump 2.97 x 2.46 x 0.5 mm Array (Top View)
1
2
3
4
5
6
7
A
B
C
D
E
F
Document No. 002-14804 Rev. *H
Page 28 of 50
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