PRELIMINARY
CYW20710
6.3.1 TCXO Clock Request Support
If the application utilizes an external TCXO as a clock reference, the CYW20710 provides a clock request output to allow the system
to power off the TCXO when not in use. Optionally, some packages support a TCXO OR function that allows a clock request in the
system to be combined with the CYW20710 clock request output, without requiring an extra component on the board.
Clock Request Output
The CLK_REQ signal on the GPIO_5 lead is asserted whenever the CYW20710 is in the Awake state. It is deasserted when in Sleep
state. When the CYW20710 is sleeping, it uses an LPO clock (external or internal) as the timing reference.
The TM0 lead controls the polarity of the CLK_REQ output on GPIO_5 as follows:
TM0 = 0 CLK_REQ is active low
TM0 = 1 CLK_REQ is active high
If the clock request feature is not desired, GPIO_5 can be configured for other functions.
TCXO OR Option
The CYW20710 has an optional feature that allows the application to perform a logical OR function on a system TCXO clock request
signal and the CYW20710 clock request to form one clock request output to the TCXO device. This logical OR function is embedded
in the pad ring so that it is available at any time, as long as the pad ring is receiving a VDDO supply. The function works even if the
CYW20710’s digital core is sleeping or completely powered off.
To use this feature, the TCXO_MODE lead must be tied high. In this mode, the GPIO_6 lead functions as the external clock request
input. Without TCXO_MODE asserted, GPIO_5 functions as the clock request output (based only on the internal clock requirements
of the CYW20710) and the state of GPIO_6 is ignored.
As mentioned earlier, the TM0 lead controls the polarity of the CLK_REQ output on GPIO_5. However, it assumes that GPIO_6 input
polarity is already consistent with the desired polarity on GPIO_5/CLK_REQ. Therefore, when TM0 is 1 for an active high output, the
function is a simple OR between the external GPIO_6 and the internal clock request state. However, when TM0 is 0 for an active low
output, the logic inverts the internal clock request signal and performs an AND between it and the GPIO_6 input. Even though it is
using an OR gate, it still provides a logical AND on the two clock request states.
Since the logic assumes that it is also active low (similar to GPIO_5 output), it does not invert the GPIO_6 input first. Table 5 shows
the truth table.
Table 5. Truth Table
GPIO_6
GPIO_5
Internal Clock Request State
(0 = sleep)
TM0
CLK_REQ_IN
(0 = active low output)
CLK_REQ
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
1
0
1
1
0
0
1
1
Document No. 002-14804 Rev. *H
Page 23 of 50
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