PRELIMINARY
CYW20710
5.4 SPI
The CYW20710 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates may be possible.
The physical interface between the SPI master and the CYW20710 consists of the four SPI signals (SPI_CSB, SPI_CLK, SPI_SI, and
SPI_SO) and one interrupt signal (SPI_INT). The CYW20710 can be configured to accept active-low or active-high polarity on the
SPI_CSB chip select signal. It can also be configured to drive an active-low or active-high SPI_INT interrupt signal. Bit ordering on
the SPI_SI and SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode, half-
duplex handshaking is implemented between the SPI master and the CYW20710.
SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload.
The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it
controls SPI_CSB and SPI_CLK. Flow control should be implemented in higher layer protocols.
Document No. 002-14804 Rev. *H
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