BCM20706 Data Sheet
Timing and AC Characteristics
PCM Interface Timing
Short Frame Sync, Master Mode
Figure 13: PCM Timing Diagram (Short Frame Sync, Master Mode)
1
2
3
PCM _BCLK
4
PCM _SYN C
PCM _OUT
8
HIGH IM PEDANCE
5
7
6
PCM _IN
Table 21: PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Reference Characteristics Minimum Typical Maximum Unit
1
2
3
4
5
6
7
8
PCM bit clock frequency
–
–
–
–
–
–
–
–
–
20.0
–
MHz
ns
PCM bit clock LOW
PCM bit clock HIGH
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
20.0
20.0
0
–
ns
5.7
5.6
–
ns
–0.4
16.9
25.0
ns
ns
PCM_IN hold
–
ns
Delay from rising edge of PCM_BCLK during last bit –0.4
period to PCM_OUT becoming high impedance
5.6
ns
Broadcom®
Bluetooth SoC
May 19, 2016 • 20706-DS202-R
Page 45
BROADCOM CONFIDENTIAL
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