BCM20706 Data Sheet
Timing and AC Characteristics
SPI Timing
The SPI interface can be clocked up to 12 MHz.
Table 18 and Figure 10 show the timing requirements when operating in SPI Mode 0 and 2.
Table 18: SPI Mode 0 and 2
Reference Characteristics
Minimum Maximum Unit
1
Time from slave assert SPI_INT to master assert SPI_CSN
(DirectRead)
0
∞
ns
2
Time from master assert SPI_CSN to slave assert SPI_INT
(DirectWrite)
0
∞
ns
3
4
5
6
Time from master assert SPI_CSN to first clock edge
Setup time for MOSI data lines
20
8
∞
ns
ns
ns
ns
1/2 SCK
1/2 SCK
100
Hold time for MOSI data lines
8
Time from last sample on MOSI/MISO to slave deassert
SPI_INT
0
7
8
Time from slave deassert SPI_INT to master deassert
SPI_CSN
0
∞
∞
ns
ns
Idle time between subsequent SPI transactions
1 SCK
Figure 10: SPI Timing, Mode 0 and 2
8
SPI_CSN
SPI_INT
(DirectWrite)
2
SPI_INT
(DirectRead)
1
3
SPI_CLK
(Mode 0)
SPI_CLK
(Mode 2)
4
5
-
First Bit
-
Second Bit
Second Bit
Last bit
Last bit
SPI_MOSI
SPI_MISO
First Bit
Not Driven
Not Driven
Table 19 and Figure 11 show the timing requirements when operating in SPI Mode 0 and 2.
Broadcom®
Bluetooth SoC
May 19, 2016 • 20706-DS202-R
BROADCOM CONFIDENTIAL
Page 42
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