BCM20706 Data Sheet
Timing and AC Characteristics
Long Frame Sync, Master Mode
Figure 15: PCM Timing Diagram (Long Frame Sync, Master Mode)
1
2
3
PCM_BCLK
4
PCM_SYNC
PCM_OUT
8
HIGH IMPEDANCE
Bit 0
Bit 0
Bit 1
Bit 1
5
7
6
PCM_IN
Table 23: PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Reference Characteristics
Minimum Typical Maximum Unit
1
2
3
4
5
6
7
8
PCM bit clock frequency
–
–
–
–
–
–
–
–
–
TBD
–
MHz
ns
PCM bit clock LOW
PCM bit clock HIGH
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
TBD
TBD
TBD
TBD
TBD
TBD
TBD
–
ns
TBD
TBD
–
ns
ns
ns
PCM_IN hold
–
ns
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
TBD
ns
Broadcom®
Bluetooth SoC
May 19, 2016 • 20706-DS202-R
Page 47
BROADCOM CONFIDENTIAL
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