The two registers that the 8051 uses to control I2C transfers are shown above. In the EZ-
USB family, an I2C interrupt request occurs on INT3 whenever the DONE bit (I2CS.0)
makes a 0-to-1 transition. This interrupt signals the 8051 that the I2C controller is ready
for another command.
The 8051 concludes I2C transfers by setting the STOP bit (I2CS.6). When the STOP con-
dition has been sent over the I2C bus, the I2C controller resets I2CS.6 to zero. During the
time the I2C controller is generating the stop condition, it ignores accesses to the I2CS and
I2DAT registers. The 8051 code should therefore check the STOP bit for zero before writ-
ing new data to I2CS or I2DAT. In the EZ-USB family, it does this by polling the I2CS.6
bit.
Page 9-16
Chapter 9. EZ-USB Interrupts
EZ-USB TRM v1.9
CYPRESS [ CYPRESS ]
