From Table 10-1, at power-on:
•
•
•
•
•
Endpoint data buffers and byte counts are un-initialized (1,2).
The 8051 is held in reset, and the CLK24 pin is enabled (3).
All port pins are configured as input ports (4-6).
USB interrupts are disabled, and USB interrupt requests are cleared (7-8).
Bulk IN and OUT endpoints are unarmed, and their stall bits are cleared (9). The
EZ-USB core will NAK IN or OUT tokens while the 8051 is reset. OUT end-
points are enabled when the 8051 is released from reset.
•
•
Endpoint toggle bits are cleared (11).
The ReNum bit is cleared. This means that the EZ-USB core, and not the 8051,
initially responds to USB device requests (12).
•
•
The USB function address register is set to zero (13).
The endpoint valid bits are set to match the endpoints used by the default USB
device (14-17).
•
Endpoint pairing is disabled. Also, ISOSend0=0, meaning that if an Isochronous
endpoint receives an IN token without being loaded by the 8051 in the previous
frame, the EZ-USB core does not generate any response (18).
•
•
The breakpoint condition is cleared, and autovectoring is turned off (19).
Configuration Zero, Alternate Setting Zero is in effect (20-21).
10.3 Releasing the 8051 Reset
The EZ-USB register bit CPUCS.0 resets the 8051. This bit is HI at power-on, initially
holding the 8051 in reset. There are three ways to release the 8051 from reset:
•
•
•
By the host, as the final step of a RAM download.
Automatically, as part of an EEPROM load.
Automatically, when external ROM is used (EA=1).
EZ-USB TRM v1.9
Chapter 10. EZ-USB Resets
Page 10-3
CYPRESS [ CYPRESS ]
