CY7C1359A/GVT71256T18
Switching Waveforms
Read Timing with Burst Feature[32, 33]
tKC
tKL
CLK
tKH
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
tH
WEL#, WEH#,
BWE#, GW#
tS
CE#
ADV#
OE#
DQ
tS
tH
tKQ
tKQ
tOEQ
tOELZ
tKQLZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Notes:
32. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active.
33. In this timing diagram, it is assumed that DEN is tied to LOW (VSS).
Document #: 38-05120 Rev. **
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