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RS8953BEPJ 参数 Datasheet PDF下载

RS8953BEPJ图片预览
型号: RS8953BEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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RS8953B/8953SPB  
4.0 Registers  
HDSL Channel Unit  
4.5 Receive Payload Mapper  
0x6B—Receive Payload Map (RMAP_6)  
7
6
5
4
3
2
1
0
RMAP[35:30]  
RMAP[35:0]  
Receive Payload Map—Six registers hold a 36-bit value to define which of the received HDSL  
payload bytes (byte1 through byte36) are placed into the RFIFO. RMAP[0] corresponds to the  
first HDSL payload byte (byte1). In T1 mode, F-bits are mapped by enabling one extra byte  
after the last payload mapped byte. For example, RMAP[12] controls F-bit mapping to the  
RFIFO in 2T1 applications.  
If RMAP[x] = 0, discard payload byte(x+1)  
If RMAP[x] = 1, map payload byte(x+1) to RFIFO  
0x67—Error Count Reset (ERR_RST)  
Writing any data value to ERR_RST clears the receive CRC Error Counter [CRC_CNT; addr 0x21], the receive  
Far End Block Error Counter [FEBE_CNT; addr 0x22], and consequently clears the Counter Overflow  
(CRC_OVR) and FEBE_OVR bits [STATUS_2; addr 0x06]. ERR_RST clears the error counters immediately  
and must be issued within 6 ms after the respective receive frame interrupt in order to avoid clearing unreported  
errors. No other receive errors (CRC_ERR, RFIFO, or RX_STUFF) are affected by ERR_RST.  
0x68—Receive Signaling Location (RSIG_LOC)  
7
6
5
4
3
2
1
0
RSIG_LOC[3:0]  
RSIG_LOC[3:0]  
Receive Signaling Location—Is applicable only if RSIG_EN [CMD_6; addr 0xF3] enables  
LTU grooming in a 2E1 or 3E1 Point-to-Multipoint (P2MP) system. The Receive Signaling  
Table [RSIG_TBL; addr 0xF2] compensates for differential frame delays between two or three  
remote sites by delaying the current PCM receive frame sync according to the RSIG_LOC  
frame delay values for each HDSL channel. RSIG_TBL uses each RSIG_LOC frame delay to  
locate frame 0 and to transfer ABCD signaling from the respective channel. RSIG_LOC sets  
the number of frame delays, from 1 to 16 frames, therefore RSIG_TBL needs to delay the  
current receive PCM frame in order to locate frame 0 of the respective channel. A value of  
zero signifies a one frame delay. A one frame delay corresponds to frame 0 occurring in the  
first HDSL payload block. RSIG_LOC values are calculated for each channel from the remote  
sites measurement of RMSYNC Phase [MSYNC_PHS; addr 0x39]:  
t(RMP)  
FRAME_LEN  
----------------------------------  
RSIG_LOC = truncate  
– 1  
where: FRAME_LEN  
RSIG_LOC  
= PCM bits per frame  
= Frame delay  
truncate []  
= Integer part only  
t(RMP)  
= Remote sites RMSYNC to MSYNC phase  
(measured in PCM bits)  
N8953BDSB  
Conexant  
4-23