欢迎访问ic37.com |
会员登录 免费注册
发布采购

RS8953BEPJ 参数 Datasheet PDF下载

RS8953BEPJ图片预览
型号: RS8953BEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
 浏览型号RS8953BEPJ的Datasheet PDF文件第76页浏览型号RS8953BEPJ的Datasheet PDF文件第77页浏览型号RS8953BEPJ的Datasheet PDF文件第78页浏览型号RS8953BEPJ的Datasheet PDF文件第79页浏览型号RS8953BEPJ的Datasheet PDF文件第81页浏览型号RS8953BEPJ的Datasheet PDF文件第82页浏览型号RS8953BEPJ的Datasheet PDF文件第83页浏览型号RS8953BEPJ的Datasheet PDF文件第84页  
4.0 Registers  
RS8953B/8953SPB  
4.2 HDSL Transmit  
HDSL Channel Unit  
TZBIT_1 is sampled on the respective transmit 6 ms frame interrupt, giving the MPU up to  
6 ms to modify the TZBIT_1 contents for output in next frame. TZBIT_2 through TZBIT_6  
are sampled during their respective output times, giving the MPU up to 1 ms after the transmit  
frame interrupt to update TZBIT_2; 2 ms to update TZBIT_3; and 5 ms to update TZBIT_6.  
This assumes all HDSL transmit frames are output aligned. If differential delay exists between  
the transmit channels (as controlled by TFIFO_WL; addr 0x05), then less time is available to  
update TZBIT_2–TZBIT_6. Unmodified registers repeatedly output their contents in each  
frame. TZBIT[0] is transmitted first.  
0x05—Transmit FIFO Water Level (TFIFO_WL)  
7
6
5
4
3
2
1
0
TFIFO_WL[7:0]  
TFIFO_WL[7:0]  
Transmit FIFO Water Level contains the number of TCLK cycles to delay from the PCM 6 ms  
frame to the start of the HDSL transmit SYNC word. A value of zero equals 1 TCLK delay.  
Minimum water level values compensate for time to unload one timeslot (8 HDSL bits), time  
to load one timeslot (8 PCM bits), the amount of differential delay created by the PCM router  
(up to 96 PCM bits in T1 mode), and a phase jitter tolerance (8 to 16 PCM bits). (Refer to  
TFIFO_WL description in the PCM Channel Section.)  
0x06—Transmit Command Register 1 (TCMD_1)  
Real-time commands (Bits 0–5) are sampled by the HOH multiplexer on the respective transmit frame to affect  
operation in the next outgoing frame. HOH_EN, TWO_LEVEL, and FORCE_ONE command bit combinations  
provide the transmit data encoding options needed to perform standard HDSL channel startup procedures.  
7
6
5
4
3
2
1
0
TX_ERR_EN  
FORCE_ONE  
HOH_EN  
SYNC_SEL  
ICRC_ERR  
TWO_LEVEL  
SCR_EN  
SCR_EN  
Scrambler Enable—All transmit HDSL channel bits, except SYNC and STUFF bits, are  
scrambled per the SCR_TAP setting in TCMD_2[0x47]. Otherwise, transmit data passes  
through the scrambler unchanged.  
0 = Scrambler bypassed  
1 = Scrambler enabled  
TWO_LEVEL  
Two Level Transmit Enable—All 2B1Q encoder magnitude bit outputs are forced to 0 to  
comply with standard requirements for a two-level transmit signal.  
0 = Four-level 2B1Q encoder operation  
1 = Two-level 2B1Q encoder operation  
ICRC_ERR  
SYNC_SEL  
Inject CRC Error—Logically inverts the six calculated CRC bits in the next frame.  
0 = Normal CRC transmission  
1 = Transmit errored CRC  
SYNC Word Select—Selects one of two SYNC words, SYNC_WORD_A or  
SYNC_WORD_B [addresses 0xCB–0xCC], for transmission in the next frame.  
0 = SYNC_WORD_A is transmitted  
1 = SYNC_WORD_B is transmitted  
4-12  
Conexant  
N8953BDSB