4.0 Registers
RS8953B/8953SPB
4.17 PRA Receive Read
HDSL Channel Unit
The register is updated twice each PCM multiframe. It increments each time a mismatch between the reported
and calculated CRC4 is detected.
The counter wraps around at 255. It is cleared/enabled by RESET_CRC_CNT of RX_PRA_CTRL1 register.
0x85—PRA Receive In-Band Code (RX_PRA_CODE)
7
6
5
4
3
2
1
0
Sa _4
Sa _3
Sa _2
Sa _1
Sa
—
—
A
6
6
6
6
5
This register is updated with a value, only if it was detected identical in the last 8 submultiframes, given the
respective field was not masked in RX_BITS_BUF1.
A
The value from the A-bit location of the data stream, in the HDSL to PCM direction.
Sa
The value from the Sa location of the data stream, in the HDSL to PCM direction.
5
5
Sa _1, _2, _3, _4 The value from the Sa _1, _2, _3, _4 location of the data stream, in the HDSL to PCM
6
6
direction.
0x86—PRA Receive Monitor Register 0 (RX_PRA_MON0)
7
6
5
4
3
2
1
0
Sa
Sa
Sa
SYNCH_STATE
—
—
CRC error2
CRC error1
8
7
4
CRC error1
Represents the CRC check result in submultiframe 1.
Represents the CRC check result in submultiframe 2.
CRC error2
Sa , Sa , and Sa
8
Updated with the value that represents the majority of identical respective bits (5 or more).
Represents the status of the multiframe synchronization machine, as follows:
4
7
SYNCH_STATE
0 = Not synchronized
1 = Synchronized
If SYNCH_STATE reads 1, the offset frame with which synchronization was achieved in
RX_MON2 is readable.
0x87—PRA Receive Monitor Register 2 (RX_PRA_MON2)
7
6
5
4
3
2
1
0
—
—
—
—
RX_PRA_MON2[3:0]
The 4 bits of this register represent the original number of the relative frame with which synchronization was
achieved. This is relevant only if bit SYNCH_STATE of RX_PRA_MON0 reads 1.
4-76
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
