RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.17 PRA Receive Read
RST_E_CNT
Clears the RX_E counter, as follows:
0 = Counter enabled
1 = Clear the E-receive counter
RST_CRC_CNT
Clears the RX_CRC counter, as follows:
0 = Counter enabled
1 = Clear the E-receive counter
NOTE:
The value of this register takes effect starting with the next PCM multiframe
following the write access cycle completion.
0x82—PRA Receive Monitor Register 1 (RX _PRA_MON1)
7
6
5
4
3
2
1
0
Sa _4
Sa _3
Sa _2
Sa _1
Sa5
A
E2
E1
6
6
6
6
The register is updated once every PCM multiframe. SA5 and A-bit are updated with a value that represents the
majority of identical corresponding bits (5 or more).
E1
E2
A
The value monitored from the E1 location of the data stream, in the HDSL to PCM direction.
E1 is the bit detected in Frame 13.
The value monitored from the E2 location of the data stream, in the HDSL to PCM direction.
E2 is the bit detected in Frame 15.
The value monitored from the A-bit location of the data stream, in the HDSL to PCM
direction.
Sa
The value monitored from the Sa location of the data stream, in the HDSL to PCM direction.
5
5
Sa _1, _2, _3, _4 The value monitored from the Sa _1, _2, _3, _4 location of the data stream, in the HDSL to
6
6
PCM direction. Sa _1, _2, _3, _4 is updated only if the same Sa6 pattern is detected in the
6
second submultiframe and synchr_en = 0.
0x83—PRA Receive E bits Counter (RX_PRA_E_CNT)
7
6
5
4
3
2
1
0
RX_PRA_E_CNT[7:0]
The register is updated twice in a PCM multiframe. It increments each time one of the E-bits is detected
active 0.
The counter wraps around at 255. It is cleared/enabled by RESET_E_CNT of RX_PRA_CTRL1 register.
0x84—PRA Receive CRC4 Errors Counter (RX_PRA_CRC_CNT)
7
6
5
4
3
2
1
0
RX_PRA_CRC_CNT[7:0]
N8953BDSB
Conexant
4-75
CONEXANT [ CONEXANT SYSTEMS, INC ]
