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RS8953SPBEPJ 参数 Datasheet PDF下载

RS8953SPBEPJ图片预览
型号: RS8953SPBEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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RS8953B/8953SPB  
4.0 Registers  
HDSL Channel Unit  
4.18 PRA Receive Write  
RST_CRC_CNT  
Clears the RX_CRC counter, as follows:  
0 = Counter enabled  
1 = Clear the E-receive counter  
NOTE:  
The value of this register takes effect starting with the next PCM multiframe,  
following the write access cycle completion.  
0xB2—PRA Receive Bits Buffer 1 (RX_BITS_BUFF1)  
7
6
5
4
3
2
1
0
Sa _MASK  
Sa _MASK  
Sa _MASK  
Sa  
Sa  
Sa  
6
6
6
8
7
4
The value of this register is only relevant if its corresponding MODE bit of RX_PRA_CTRL0 is set. A new  
written value takes effect starting with the next PCM multiframe following the register write access cycle  
completion.  
An in-band code is reported as detected when the pattern in the Sa , Sa , AND A fields remain constant for 8  
6
5
consecutive multiframes.  
Sa  
Sa  
Sa  
The new value to be inserted into the Sa location of the data stream, in the HDSL to PCM  
direction.  
4
7
8
4
The new value to be inserted into the Sa location of the data stream, in the HDSL to PCM  
7
direction.  
The new value to be inserted into the Sa location of the data stream, in the HDSL to PCM  
8
direction.  
A_MASK  
Determines if the pattern in the A-bit field must remain constant for 8 consecutive multiframes  
for an in-band code to be reported as detected.  
SA _MASK  
Determines if the pattern in the SA field must remain constant for 8 consecutive multiframes  
5
5
for an in-band code to be reported as detected.  
SA _MASK  
Determines if the pattern in the SA field must remain constant for 8 consecutive multiframes  
6
6
for an in-band code to be reported as detected.  
0xB4—PRA Receive Bits Buffer 0 (RX_BITS_BUFF0)  
7
6
5
4
3
2
1
0
Sa _4  
Sa _3  
Sa _2  
Sa _1  
Sa5  
A
E2  
E1  
6
6
6
6
The value of this register is only relevant if the corresponding MODE bit of RX_PRA_CTRL0 is set. A new  
written value takes effect starting with the next PCM multiframe, following the register write access cycle  
completion. Each bit of this register is used in the odd frames of the PCM multiframe.  
E1  
E2  
A
The new value to be inserted into the E1 location of the data stream, in the HDSL to PCM  
direction. E1 is used in Frame 13.  
The new value to be inserted into the E2 location of the data stream, in the HDSL to PCM  
direction. E2 is used in Frame 15.  
The new value to be inserted into the A-bit location of the data stream, in the HDSL to PCM  
direction. A-bit is used in all odd frames.  
N8953BDSB  
Conexant  
4-79  
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