RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.16 PRA Transmit Write
4.16 PRA Transmit Write
Table 4-13. PRA Transmit Write Registers
Address
Register Label
Bits
Name/Description
0x70
0x71
0x72
0x73
0x74
TX_PRA_CTRL0
TX_PRA_CTRL1
8
7
6
8
8
PRA Transmit Control Register 0
PRA Transmit Control Register 1
PRA Transmit Bits Buffer 1
TX_BITS_BUFF1
TX_PRA_TMSYNC_OFFSET
TX_BITS_BUFFO
PRA Transmit TMSYNC Offset Register
PRA Transmit Bits Buffer 0
0x70—PRA Transmit Control Register 0 (TX_PRA_CTRL0)
7
6
5
4
3
2
1
0
E_MODE[1:0]
SA8_MODE
SA7_MODE
SA6_MODE[1:0]
SA5_MODE
SA4_MODE
SA4_MODE
SA5_MODE
SA6_MODE
Controls the behavior of Sa4 bits transmitted towards the HDSL link, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of Sa5 bits transmitted towards the HDSL link, as follows:
0 = Transparent
1 = From bits buffer 0
Controls the behavior of Sa6 bits transmitted towards the HDSL link, as follows:
Code
00
01
Sa6 Bits
Transparent
From bits buffer 0
Automatic
10
11
Illegal
The Automatic mode operates based on the result of the receiver (HDSL to PCM) CRC
check and E-bits, as follows:
Received E-bits
0 (Error)
Receive CRC Checks
Error
Sa6
0011
0 (Error)
1 (No Error)
1 (No Error)
No Error
Error
No Error
0001
0010
From bits buffer 0 (sec 0)
NOTE:
MSB of Sa6 is transmitted first (i.e., in frames 1 and 9).
SA7_MODE
Controls the behavior of Sa7 bits transmitted towards the HDSL link, as follows:
0 = Transparent
1 = From bits buffer 1
N8953BDSB
Conexant
4-69