RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.14 Common Status
0x38—DPLL Phase Error (PHS_ERR)
7
6
5
4
3
2
1
0
PHS_ERR[7:0]
PHS_ERR[7:0]
DPLL Phase Error—The DPLL phase detector error output is given in 2’s complement format
in units of GCLK cycles, where minimum (negative) phase is reported as 0x80 and maximum
(positive) phase as 0x7F. The result of the PCM to HDSL 6 ms phase comparison is updated
coincident with the RXn interrupt (where n = master HDSL channel number). During DPLL
closed loop operation, the phase error’s long term average equals zero. PHS_ERR is provided
for diagnostic testing only.
0x39—Multiframe Sync Phase Low (MSYNC_PHS_LO)
7
6
5
4
3
2
1
0
MSYNC_PHS[7:0]
0x3A—Multiframe Sync Phase High (MSYNC_PHS_HI)
7
6
5
4
3
2
1
0
—
—
—
MSYNC_PHS[12:8]
MSYNC_PHS[12:0] Multiframe Sync Phase—Contains the number of elapsed TCLK cycles measured from the
rising edge of the TMSYNC or the RMSYNC signal selected by MSYNC_MEAS [CMD_6;
addr 0xF3] to the rising edge of MSYNC. A value of zero indicates the phase equals 1 TCLK
cycle. Maximum phase equals 1 PCM multiframe. For example, Nx64 multiframe equals 16
frames times [N = 64 the timeslots per frame, times 8 bits per timeslot, for a total length equal
to 8,192 PCM bits (0x1FFF].
For unframed or asynchronously mapped applications, knowing the TMSYNC to MSYNC
phase simplifies far-end reconstruction of RMSYNC. Therefore, each terminal measures
TMSYNC phase, and sends it to the far-end for calculation of the RFRAME_LOC [addr
0xC3] and the RMF_LOC [addr 0xC5] delays needed to recreate RMSYNC. TMSYNC phase
measurement is unnecessary when PCM and HDSL frames are synchronized or the far-end
does not need to create RMSYNC.
t(TMP)
FRAME_LEN
----------------------------------
RMF_LOC.RFRAME_LOC =
where: FRAME_LEN = Bits per frame [FRAME_LEN; address
0xC8]
RMF_LOC
RFRAME_LOC = Bit delay (fractional part of result)
t(TMP)
= TMSYNC to MSYNC Phase (in PCM bits)
= Frame delay (integer part of result)
N8953BDSB
Conexant
4-63
CONEXANT [ CONEXANT SYSTEMS, INC ]
