RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.14 Common Status
0x1E—BER Status (BER_STATUS)
7
6
5
4
3
2
1
0
—
—
—
—
—
SYNC_DONE
BER_DONE
BER_SYNC
BER_SYNC
BER Pattern SYNC—Applicable only if SYNC_DONE is active. BER_SYNC reports
whether the BER meter acquired test pattern sync during the 128-bit test pattern qualification
period. The BER meter must detect fewer than 8 bit errors during examination of the first 128
bits to assert BER_SYNC. BER_SYNC can report a false pattern sync if all 1s or all 0s are
applied.
0 = No pattern sync
1 = Pattern sync detected
BER_DONE
BER Measurement Complete—Signifies the BER meter has completed examination of the
total number of test pattern bits programmed by BER_SCALE. When BER_DONE is set, the
BER meter stops counting bit errors.
0 = BER measurement in progress
1 = BER measurement complete
SYNC_DONE
Sync Qualification Period Complete—Indicates the BER meter has examined 128 bits and has
updated BER_SYNC. SYNC_DONE reports the end of the test pattern qualification period.
0 = Qualification period in progress
1 = Qualification period complete
0x1F—Interrupt Request Register (IRR)
The INTR* output pin is activated and the corresponding IRR bit latched whenever an interrupt event transition
is detected from one of eight sources. Interrupt sources that are masked [see IMR; addr 0xEB] do not activate
the INTR* output but are latched and reported in the IRR. Latched IRR bits are reset and the INTR* output is
deactivated by writing a 0 to the corresponding Interrupt Clear Register bits [ICR; addr 0xEC]. However, if IRR
is reporting a persistent error condition such as framer OUT_OF_SYNC, then writing ICR deactivates the
INTR* pin, but does not clear the IRR bit unless the error condition has ended. INTR* output activation is
triggered by an event edge; therefore, persistent or multiple error conditions only generate one INTR* request.
7
6
5
4
3
2
1
0
RX_ERR
TX_ERR
RX[3:1]
TX[3:1]
TX1-TX3
Transmit HDSL 6 ms Frame Interrupt—Reported coincident with the start of the transmit
6 ms frame for the respective HDSL channel. This allows the MPU to synchronize read access
of the transmit status [STATUS_3; addr 0x07] and to synchronize write access to the real time
transmit HDSL registers (see Table 4-2).
0 = No interrupt
1 = Transmit frame interrupt
N8953BDSB
Conexant
4-61
CONEXANT [ CONEXANT SYSTEMS, INC ]
