RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.13 Receive/Transmit Status
CRC_CNT[7:0]
CRC Error Count—Indicates the total number of received CRC errors detected by the receive
framer, and increments by one for each received HDSL 6 ms frame that contains CRC_ERR
[STATUS_1; addr 0x06]. CRC_CNT is cleared to 0 by ERR_RST [addr 0x67]. Error counting
is suspended while the receive framer is OUT_OF_SYNC or SYNC_ACQUIRED. CRC_CNT
also sets CRC_OVR [STATUS_2; addr 0x06] upon reaching its maximum count value of 255.
0x22—Far End Block Error Count (FEBE_CNT)
7
6
5
4
3
2
1
0
FEBE_CNT[7:0]
FEBE_CNT[7:0]
Far-End Block Error Count—Indicates the total number of received FEBE errors sent by the
far-end transmitter and increments by 1 for each received HDSL 6 ms frame that contains an
active FEBE bit. The polarity of active FEBE is determined by FEBE_POLARITY in CMD_7
(addr 0xF4). FEBE is the second IND bit received within the indicator bit group and can be
monitored separately as the RIND[1] bit in the RIND_LO [addr 0x02] receive status register.
Refer to Table 3-2 for the FEBE bit position within the frame. FEBE_CNT is reset to 0 by
ERR_RST [addr 0x67]. Error counting is suspended while the receive framer is
OUT_OF_SYNC or SYNC_ACQUIRED. FEBE_CNT also sets FEBE_OVR [STATUS_2;
addr 0x06] upon reaching its maximum count value of 255.
N8953BDSB
Conexant
4-59
CONEXANT [ CONEXANT SYSTEMS, INC ]
