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RS8953SPBEPJ 参数 Datasheet PDF下载

RS8953SPBEPJ图片预览
型号: RS8953SPBEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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4.0 Registers  
RS8953B/8953SPB  
4.13 Receive/Transmit Status  
HDSL Channel Unit  
0x07—Transmit Status (STATUS_3)  
7
6
5
4
3
2
1
0
STUFF_ERR  
TFIFO_SLIP  
TFIFO_MPTY  
TFIFO_FULL  
TX_STUFF  
TX_STUFF  
Transmit STUFF Decision—Indicates whether the last transmitted HDSL frame was output  
with 4 STUFF bits or none.  
0 = No STUFF bits output  
1 = 4 STUFF bits output  
TFIFO_FULL  
Transmit FIFO Full Error—Indicates the TFIFO has overflowed. This is also reported in  
ERR_STATUS and IRR (if TX_ERR_EN in TCMC_1[addr0x06]) and generates a TX_ERR  
interrupt (if TX_ERR in IMR is enabled). TFIFO_FULL errors may result from a change of  
transmit PCM frame alignment when MPU writes to TFIFO_RST, or from any changes in  
TCLK or BCLKn frequency or to the transmit routing table or the transmit payload map.  
0 = TFIFO normal  
1 = TFIFO overflowed  
TFIFO_MPTY  
TFIFO_SLIP  
Transmit FIFO Empty Error—Indicates the TFIFO has Underrun. This is also reported in  
ERR_STATUS and IRR (if TX_ERR_EN in TCMC_1[addr0x06]), and generates a TX_ERR  
interrupt (if TX_ERR in IMR is enabled). TFIFO_MPTY errors may be triggered by events  
similar to those which cause TFIFO_FULL errors.  
0 = TFIFO normal  
1 = TFIFO Underrun  
Transmit FIFO Slip—Indicates that the number of PCM timeslots routed into the TFIFO is not  
equal to the number of payload bytes mapped out of the TFIFO over a 6 ms period. This is also  
reported in ERR_STATUS and IRR (if TX_ERR_EN in TCMC_1[addr0x06]), and generates a  
TX_ERR interrupt (if TX_ERR in IMR is enabled). TFIFO_SLIP errors may be triggered by  
events similar to those which cause TFIFO_FULL errors. Repeated TFIFO_SLIP errors may  
indicate improper configuration of either the transmit payload map or the transmit routing  
table.  
0 = Transmit FIFO normal  
1 = Transmit FIFO unbalanced  
STUFF_ERR  
Transmit Stuffing Error—Indicates when the phase difference measured from PCM to HDSL  
6 ms frames exceeds the maximum bit Stuffing Threshold [STF_THRESH_C; addr 0xD3].  
This is also reported in ERR_STATUS and IRR (if TX_ERR_EN) and generates a TX_ERR  
interrupt (if TX_ERR in IMR is enabled). STUFF_ERR may be triggered by events similar to  
those which cause TFIFO_FULL errors. The STUFF generator is automatically reset when  
STUFF_ERR is detected.  
0 = STUFF generator normal  
1 = STUFF generator error  
0x21—CRC Error Count (CRC_CNT)  
7
6
5
4
3
2
1
0
CRC_CNT[7:0]  
4-58  
Conexant  
N8953BDSB  
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