RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.13 Receive/Transmit Status
0x18—Receive Z-Bits (RZBIT_2)
7
6
5
4
4
4
4
4
3
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
RZBIT[15:8]
RZBIT[23:16]
RZBIT[31:24]
RZBIT[39:32]
RZBIT[47:40]
0x19—Receive Z-Bits (RZBIT_3)
7
6
5
0x1A—Receive Z-Bits (RZBIT_4)
7
6
5
0x1B—Receive Z-Bits (RZBIT_5)
7
6
5
0x1C—Receive Z-Bits (RZBIT_6)
7
6
5
RZBIT[47:0]
Receive Z-bits—Applicable only in E1_MODE [CMD_1; addr 0xE5]. RZBIT holds 48 Z–bits
received during the previous HDSL frame. Refer to Figures 3-21 and 3-26 for Z–bit positions
within the frame. The LSB RZBIT[0] is received first. The first 8 received Z-bits from each
HDSL channel are individually monitored in the RZBIT_1 registers. The last 40 received
Z-bits are monitored in the RZBIT_2–RZBIT_6 registers from only the single receive channel
selected by ZBIT_SEL [CMD_5; addr 0xE9]. Systems which need individual channel
monitoring of the last 40 Z-bits can use external circuitry to capture the Z-bits from the receive
HDSL auxiliary channel (RAUXn) outputs.
0x05—Receive Status 1 (STATUS_1)
7
6
5
4
3
2
1
0
MAJOR_VER[1:0]
RFIFO_SLIP
RFIFO_MPTY
RFIFO_FULL
RX_STUFF
TR_INVERT
SYNC_AB
N8953BDSB
Conexant
4-55
CONEXANT [ CONEXANT SYSTEMS, INC ]
