RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.12 Interrupt and Reset
4.12 Interrupt and Reset
Table 4-9. Interrupt and Reset Write Registers
Address
Register Label
Bits
Name/Description
0xEB
0xEC
0xEF
0xF0
0xF1
IMR
ICR
8
Interrupt Mask Register
Interrupt Clear Register
8
BER_RST
PRBS_RST
RX_RST
—
—
—
Reset BER Meter/Start BER Measurement
Reset PRBS Generator
Reset Receiver
0xEB—Interrupt Mask Register (IMR)
The MPU writes a 1 to an IMR bit to mask the respective interrupt event. Masked interrupt sources are
prevented from generating an active low signal on the INTR* output, but are reported in the Interrupt Request
Register (IRR). Writing zero to the IMR bit enables the respective interrupt event to generate an active low
signal on the INTR* output. Upon power-up or RST* assertion, all IMR bits are automatically set to 1 to disable
the INTR* output.
7
6
5
4
3
2
1
0
RX_ERR
TX_ERR
RX[3:1]
TX[3:1]
TX1–TX3
Mask the HDSL 6 ms transmit frame interrupt for the respective channel.
Mask the HDSL 6 ms receive frame interrupt for the respective channel.
Mask the HDSL transmit error interrupt.
RX1–RX3
TX_ERR
RX_ERR
Mask the HDSL receive error interrupt.
0xEC—Interrupt Clear Register (ICR)
The MPU writes a zero to an ICR bit to reset the respective IRR bit and, if all IRR bits are 0, causes the INTR*
output to enter a high impedance state. Writing a 1 has no effect.
7
6
5
4
3
2
1
0
RX_ERR
TX_ERR
RX[3:1]
TX[3:1]
TX1–TX3
Clear the HDSL 6 ms transmit frame interrupt for the respective channel.
Clear the HDSL 6 ms receive frame interrupt for the respective channel.
Clear the HDSL transmit error interrupt.
RX1–RX3
TX_ERR
RX_ERR
Clear the HDSL receive error interrupt.
N8953BDSB
Conexant
4-51
CONEXANT [ CONEXANT SYSTEMS, INC ]
