4.0 Registers
RS8953B/8953SPB
4.11 Common Command
HDSL Channel Unit
0xE7—Command Register 3 (CMD_3)
7
6
5
4
3
2
1
0
RSIG_WR
PRBS_MODE[1:0]
BER_SCALE[1:0]
PRBS_DIS
ROUTE_EN
COMB_EN
COMB_EN
Enable Receive Combination Table Access—The write pointer for the combination table
[COMBINE_TBL; addr 0xEE] is reset to 0, and table access is enabled. MPU writes to
COMBINE_TBL are ignored when COMB_EN is low.
0 = Disable access to COMBINE_TBL
1 = Enable MPU access to COMBINE_TBL and reset write pointer
ROUTE_EN
Enable Transmit Routing Table Access—The write pointer for the transmit routing table
[ROUTE_TBL; addr 0xED] is reset to 0, and table access is enabled. MPU writes to
ROUTE_TBL are ignored when ROUTE_EN is low.
0 = Disable access to ROUTE_TBL
1 = Enable MPU access to ROUTE_TBL and reset write pointer
PRBS_DIS
PRBS Disable—Replaces PRBS generator output with data from the Fill Pattern Register
[FILL_PATT; addr 0xEA]. Fill patterns are routed to the transmit FIFO in the same manner as
PRBS patterns.
0 = PRBS generator output enabled
1 = Fill Pattern replaces PRBS data
BER_SCALE[1:0]
BER Meter Scale—Selects the test interval over which bit errors are accumulated by the BER
Meter [BER_METER; addr 0x1D]. The test interval is counted only during bits selected and
checked by the BER meter. See also BER_SEL [CMD_6; addr 0xF3].
BER_SCALE
00
Test Interval
231 bits
Approximate Scale
2 x 109
228 bits
225 bits
2 x 108
3 x 107
2 x 106
01
10
11
2
21 bits
NOTE:
The time to complete the test interval depends on the number of bytes examined in
each frame, where total test time may exceed 9 hours and 19 minutes.
PRBS_MODE[1:0] Pseudo-Random Bit Sequence Length—Establishes the LFSR pattern generated by the
transmit PRBS generator and checked by the receive BER meter. There is an inverter in the
15
data path when the 2 test pattern is selected.
PRBS_MODE
00
Test Pattern
LFSR Tap Selection
1 + x18 + x23
223
220 (14-zero limit)
1 + x17 + x20
1 + x14 + x15
1 + x3 + x4
01
10
11
215
24
RSIG_WR
Enable Receive Signaling Table Access—The write pointer for the Receive Signaling Table
[RSIG_TBL; addr 0xF2] is reset to 0, and table access is enabled. MPU writes to RSIG_TBL
are ignored when RSIG_WR is low.
0 = Disable access to RSIG_TBL
1 = Enable MPU access to RSIG_TBL and reset write pointer
4-46
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
