CX82100 Home Network Processor Data Sheet
qwords is determined by DMA_{x}_Cnt2. If there are N cluster descriptors then the
value 2N should be written to DMA_{x}_Cnt2.
The DMAC prefetches the cluster pointers to a two-pointer queue using a source DMA
channel. This queue is initialized (filled) automatically as soon as the firmware writes to
DMA_{x}_Cnt2 (so CDT must be valid and DMA_{x}_Ptr2 initialized). The DMAC has
a two-pointer queue in order to reduce the latency seen by the EMAC-RxD channel when
switching from one cluster to another. The DMAC does not want to add the cluster
pointer fetch latency to the data transfer latency. The current pointer in the queue is
DMA_{x}_Ptr1 and points to the location in the cluster buffer where the received data is
to be stored. This pointer can be read anytime.
The DMA_{x}_Cnt1 value is used to limit the number of qwords the EMAC-RxD can
write to the cluster buffer. Writing a value X to this register will cause all qwords DMA
transferred past X to be stored in the same cluster location (overwritten, only last qword
visible). Reading this register will return a value that indicates the number of qwords
transferred which could be even larger than the size written to DMA_{x}_Cnt1. This
register limits how far the DMA_{x}_Ptr1 may advance. The DMA_{x}_Cnt1 value
increments by 1 for each DMA_XNXT as well as DMA_XNUL.
The EMAC-RxD DMA channel uses a state machine to control the interactions of the
firmware, EMAC-RxD DMA requests, and the DMAC. This state machine is initialized
when DMA_{x}_Cnt2 is written. This event triggers the prefetch of two cluster pointers
from the CDT. The DMA_{x}_Ptr2 will be pointing to the first EMAC-RxD status
qword location after it fills its DMA_{X}_Ptr1 queue. When the EMAC-RxD channel
issues DMA_XSAV, the packet status is read and transferred to the current
DMA_{X}_Ptr2 location. The receiver channel then issues DMA_INTR which causes
the packet interrupt. It also triggers this state machine to transfer the prefetched cluster
pointer to DMA_{X}_Ptr1 and then prefetch the next cluster pointer.
At the beginning of each packet the EMAC-RxD channel issues a DMA_SAVE to save a
copy of the DMA_{X}_Ptr1 cluster head pointer. In case of a bad packet (too short, bad
CRC, etc.) the EMAC-RxD channel will abort the packet and issue a DMA_RELD. This
event will cause the copy of the cluster head pointer to be reloaded into DMA_{X}_Ptr1
and the DMA_{X}_Cnt1 to be re-initialized to zero.
The clusters (received packets) consist of received data qwords transferred via
DMA_XNXT surrounded by reserved qwords at the head and tail of the buffers.
Table 4-5. Received Data Packet
qword No.
Cluster qword ⇐ DMA_{x}_Ptr1, {x} = 2 or 4
Reserved < DMA_XNUL
1
2
P-1
P
…
X
X+1
EMAC-RxD < DMA_XNXT
EMAC-RxD < DMA_XNXT
Reserved (0) < DMA_XNXT
…
Maximum length of packet data
Overflow location for too long packet
The 1st reserved qword is present because the EMAC-RxD channel issues a
DMA_XNUL at the beginning of every packet. The last reserved qword results from the
channel issuing a DMA_XNXT to transfer a zero qword. If DMA_{X}_Cnt1 is set to X,
then all qwords received after that limit for a given packet will be transferred to location
DMA_{X}_Ptr1 + 8(X+1). The DMA_XNUL does increment DMA_{X}_Cnt1. Most
packets will end much shorter than the programmed limit. In the case of a too long
received packet, the EMAC will end up aborting the packet which causes the next packet
4-8
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